The present invention relates to a bus control system for use in a data processing apparatuses such as a personal computer and a work station, and in particular, to improvement of a bus control system supporting a so-called split transfer protocol in which between a start cycle of an access operation of a processor and a response cycle for the access operation from an input/output (I/O) device related thereto, it is possible to insert on an identical bus a start cycle of an access operation of another processor.
As a bus like a conventional system bus, there has been used in many cases a bus supporting the split transfer protocol, for example, as described in "Futurebus+, P896.1, Logical Layer Specifications" (1990, IEEE). This is because that the utilization efficiency and the response time of the bus are improved.
FIG. 15 shows an example of a typical timing of the split transfer protocol. In this chart, ADDT[0-63] stands for an address/data bus on which 8-byte (64-bit) addresses and data are multiplexed, ADRV denotes an address valid signal indicating that an effective address is being outputted onto the bus ADDT, and DATAV designates a data valid signal indicating that an effective data item is being outputted onto the bus ADDT.
Referring to FIG. 15, description will be given of a conventional read and access operation to obtain data. First, a module (for example, a processor) initiating a read access operation acquires a bus mastership of the bus ADDT. The module then enables the signal ADRV and outputs an address specifying a module to be accessed onto the bus ADDT. At the same time, the initiating module notifies that the access being initiated is a split read access to the destination module (for example, a bus adapter connected to a plurality of I/O devices) via a mode specification control signal line CONT (at a timing 1301 of FIG. 15). Thereafter, the source module renounces or releases the bus mastership to terminate the start cycle.
On the other hand, the destination module designated by the address obtains the mastership of the bus ADDT when read data becomes ready for the access. The destination module then enables the signal ADRV and sends an address specifying a module to be accessed onto the bus ADDT. That is, it is to be noted that the same address is outputted onto the bus ADDT from the source and destination modules. Simultaneously, the initiating module reports the terminating module via the line CONT that the access being initiated is a response to the split read access (at a timing 1302 of FIG. 15). Subsequently, the data valid signal DATAV is enabled and an effective data item is outputted onto the bus ADDT[0-63]. The destination module then releases the bus mastership and terminates the response cycle.
The source module checks the contents on the line CONT and the access destination address on the bus ADDT to determine that the data is sent in response to the initiated access operation so as to get the response data.
However, as above, in a case where there is disposed a cycle in which the access destination address is outputted onto the bus ADDT when the response data is transferred in response to a split read access, the ratio of busy time of the bus in which the bus is being occupied for operation is increased. Recently, there has been an increase in the number of systems in which, also for minimization of the size and price, the number of signal lines of the bus is decreased, particularly, address and data lines are multiplexed in the bus. In such a multiplex bus, the increase in the busy ratio of bus is an essential problem because of deterioration in the bus utilization efficiency and increase in the response time.
Moreover, due to the recent growing volume of data to be processed, the number of address lines is also increased. In consequence, according to the method above, there exists a problem that the number of flip-flop circuits to keep therein addresses specifying access destination items is increased and hence the hardware system of each module becomes to be more complex.